Boundary scan refers to a technique for testing a circuit to detect problems with interconnects and circuit components. Detected problems include open or short circuits, dead or missing components, and faulty integrated circuit blocks. Boundary scan is performed by driving a test signal onto an interconnect being tested, and reading the output of a boundary scan receiver located at the far-end of the interconnect. The output may indicate that the path between the input pin and the output pin is open, shorted, or faulty, e.g., when the value or values of the output signal are not as expected based on the test signal. The interconnect attached to each input pin of the circuit may be tested in this manner, with appropriate test signals or test patterns being applied.
Boundary scan has been developed by the Joint Test Action Group (“JTAG”) and is incorporated into the Institute of Electrical and Electronics Engineers (“IEEE”) standard 1149.6. The standard provides for the testing of circuits that use differential signaling and alternating current (“AC”) coupling. AC and direct current (“DC”) testing modes are both supported. On the input side, the test circuit is referred to as a driver. On the output side, the test circuit is referred to as a receiver. In the AC mode, the receiver reconstructs the signal sent by the transmitter by detecting positive and negative edges. AC detection involves comparing the output against two thresholds (a positive threshold and a negative threshold) to identify when the output crosses either threshold. AC detection may be performed, for example, using two comparators—one with a reference level corresponding to the positive threshold and another one with a reference level corresponding to the negative threshold. In the DC mode, the receiver directly detects the signal level of the output, also using a threshold comparison, but without detecting edges. In IEEE 1149.6, the receiver includes an output capturing device in the form of a flip-flop that is initialized by presetting the flip-flop to a known value.
A receiver according to IEEE 1149.6 may include a flip-flop whose set and reset (clear) inputs are separately controlled by an output of a corresponding comparator. The output of the flip-flop, which is also the output of the receiver, will depend on how the flip-flop is set and reset by the comparators. The comparators may each have a first data input connected to an input of the receiver through respective offset voltages. The offset voltages determine the reference levels of the comparators and provide voltage hysteresis. Second data inputs of the comparators may be connected to a delayed and low pass filtered version of the input. In the AC mode, the comparators are not connected to a fixed voltage reference. Instead, the low-pass filter essentially provides an average history of the input, against which history the current input is compared.
The receiver described above can be modified to support DC mode by adding a switch that disconnects the low pass filter to instead connect a fixed reference voltage to the second data inputs of the comparators, and by changing the voltage offsets to a value suitable for DC level detection. In the AC mode, the comparators would need to compare the input voltage for a minimum period of time known as a hysteresis delay. The hysteresis delay is chosen to be significantly longer than the expected transition time of the input. Each comparator should output a decision (logic level 1 or 0) only after this minimum period has elapsed. If the input was continuously greater than the reference voltage plus the offset voltage, the comparator outputs a 1. If the input was continuously less than the reference voltage minus the offset voltage, the comparator outputs a 0. If the input is in-between these two reference levels (i.e., less than the reference voltage plus the offset voltage, and greater than the reference voltage minus the offset voltage), the comparator maintains its current output state.
A differential boundary scan test setup may include a differential driver that is AC coupled to a receiver unit. The driver is connected to an input pin of a circuit being tested and the receiver unit is connected to a corresponding output pin of the circuit. Each polarity of a differential AC signal output by the circuit being tested in response to the driver forms an input to a corresponding receiver circuit in the receiver unit. The outputs of these receiver circuits together form a differential digital output that could be analyzed for circuit errors. If the individual receiver circuits are the same as the IEEE 1149.6 receiver described above, then two comparators would be needed for each polarity of the differential AC signal, four comparators in total.